A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme

Author

Johguchi, Koh ; Mukuda, Yuya ; Izumi, Shinya ; Mattausch, Hans Jürgen ; Koide, Tetsushi

Author_Institution

Hiroshima Univ., Hiroshima

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

320

Lastpage

323

Abstract

A 8-read, 8-write port, 64-Kbit, 32-bit word-length SRAM design with multi-bank architecture is reported. Using a 2-stage-pipeline, a multi-stage-sensing scheme and a 2-port SRAM cell, high speed and high stability access is achieved simultaneously. The fabricated test chip in 90-nm CMOS technology features 1.2 GHz maximum clock frequency, 0.91 mm Si-area, 0.6 Tbps random-access bandwidth, and 123 mW power dissipation at 1.2 GHz. In comparison with a previously reported 16-port SRAM a bit-area reduction by an order of magnitude is achieved.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit design; logic design; multiport networks; 2-port SRAM cell; 2-stage-pipeline sensing scheme; CMOS technology; SRAM design; bit rate 0.6 Tbit/s; frequency 1.2 GHz; multibank architecture; multistage-sensing scheme; power 123 mW; size 90 nm; storage capacity 84 Kbit; word length 32 bit; Bandwidth; CMOS technology; Decoding; Frequency; Memory architecture; Microprocessors; Pipelines; Power dissipation; Random access memory; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Conference_Location

Munich

ISSN

1930-8833

Print_ISBN

978-1-4244-1125-2

Type

conf

DOI

10.1109/ESSCIRC.2007.4430308

Filename

4430308