Title :
A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS
Author :
Pellerano, Stefano ; Palaskas, Yorgos ; Soumyanath, Krishnamurthy
Author_Institution :
Intel Corp., Hillsboro
Abstract :
This paper presents an integrated LNA for mm-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for "correct-by-construction" design at mm-wave frequency and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with an NF of 6.5 dB, while drawing 26 mA per stage from 1.65 V. Output P1dB is 3.8 dBm. At VDD = 1.26 V, each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB respectively. To the authors\´ knowledge, this is the lowest measured NF at mm-wave frequencies reported so far in CMOS. Measured results are in excellent agreement with simulations. A custom set-up for mm- wave NF measurement is also extensively described in the paper.
Keywords :
CMOS analogue integrated circuits; integrated circuit design; integrated circuit measurement; integrated circuit modelling; low noise amplifiers; millimetre wave amplifiers; CMOS technology; RC parasitic extraction; correct-by-construction design; current 19 mA; current 26 mA; device measurements; dual-stage cascode LNA; electromagnetic simulations; frequency 64 GHz; gain 13.5 dB; gain 15.5 dB; low noise amplifier; mm-wave applications; mm-wave frequency; noise figure 6.5 dB; noise figure 6.7 dB; size 90 nm; voltage 1.26 V; voltage 1.65 V; CMOS technology; Coplanar transmission lines; Coplanar waveguides; Frequency measurement; Gain; Noise measurement; Power transmission lines; Semiconductor device modeling; Silicon; Wideband;
Conference_Titel :
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1125-2
DOI :
10.1109/ESSCIRC.2007.4430316