DocumentCode
2771998
Title
A pipelined serial data receiver with oversampling techniques for high-speed data communications
Author
Lin, Yih-Homg ; Tu, Steve Hung-Lung
Author_Institution
Dept. of Electron. Eng., Fu-Jen Catholic Univ., Taipei, Taiwan
fYear
2003
fDate
16-18 Dec. 2003
Firstpage
167
Lastpage
170
Abstract
In this paper, we propose a novel oversampling receiver to achieve NRZI (Non-Return-to-Zero-Inverted) data recovery for serial link communications. Adopting feed-forward not conventional PLL (Phase-Locked Loop) feed-back operation is quite suitable for high-bandwidth applications. The employment of byte-level pipelined architecture greatly reduces the complexity of the system clock configuration. Moreover, the characteristic of high data deviation tolerance was indicated from the experimental results.
Keywords
data communication equipment; phase locked loops; NRZI data recovery; PLL feed-back operation; byte-level pipelined architecture; data deviation tolerance; high-bandwidth applications; high-speed data communications; oversampling receiver; phase-locked loop; pipelined serial data receiver; serial link communications; Circuits; Clocks; Data communication; Data mining; Decoding; Distortion measurement; Feedforward systems; Frequency; Phase locked loops; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN
0-7803-7749-4
Type
conf
DOI
10.1109/EDSSC.2003.1283507
Filename
1283507
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