• DocumentCode
    2772068
  • Title

    1.25-Gb/s 0.25-μm CMOS clock recovery based on phase- and frequency-locked loop

  • Author

    Hu, Yan ; Wang, Zhi-Gong

  • Author_Institution
    Inst. of RF-&OE-ICs, Southeast Univ., Nanjing, China
  • fYear
    2003
  • fDate
    16-18 Dec. 2003
  • Firstpage
    179
  • Lastpage
    182
  • Abstract
    A 1.25-Gb/s clock recovery (CR) circuit for Very Short Reach (VSR) OC-192/STM-64 parallel optics interface is realized based on a phase- and frequency-locked loop. The test CR IC achieves a wide locking range from 1.03 GHz to 1.42 GHz, a small rms jitter of 4.62 ps (0.00368 UI) for a pseudorandom bit sequence (PRBS) length of 231-1. The DC consumption is 132 mW.
  • Keywords
    CMOS digital integrated circuits; digital phase locked loops; frequency locked loops; jitter; random sequences; synchronisation; 0.25 micron; 1.03 to 1.42 GHz; 1.25 Gbit/s; 132 mW; 4.62 ps; CMOS clock recovery circuit; FLL; PLL; frequency-locked loop; parallel optics interface; phase locked loop; power dissipation; pseudorandom bit sequence; rms jitter; wide locking range; Chromium; Circuits; Clocks; Delay; Frequency locked loops; Jitter; Optical filters; Phase detection; Phase frequency detector; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
  • Print_ISBN
    0-7803-7749-4
  • Type

    conf

  • DOI
    10.1109/EDSSC.2003.1283510
  • Filename
    1283510
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2772068