Embedded SRAM design in deep deep submicron technologies

Static RAM memory is more than ever a key component in systems on chip. Static memories are dominating factors in the cost, the performance and the energy consumption of such systems. Deep deep submicron scaling beyond 130 nm complicates the design of SRAM circuits that make a good compromise between performance and energy consumption. This is mainly caused by leakage and technological variability. The effect of leakage and variability is amplified by the fact that large area penalties are unacceptable for cost reasons. As a consequence, novel circuit designs are needed to alleviate the additional problems introduced by advanced scaling while keeping classic scaling advantages intact. This paper gives an overview of circuit techniques that have recently been proposed to improve the position of SRAMS in the area-energy-performance design space. This paper starts from the SRAM cell, expands to the local bitline to conclude with the circuit architecture of complete SRAMs.