Title :
Layout options for stability tuning of SRAM cells in multi-gate-FET technologies
Author :
Bauer, F. ; Von Arnim, K. ; Pacha, C. ; Schulz, T. ; Fulde, M. ; Nackaerts, A. ; Jurczak, M. ; Xiong, W. ; San, K.T. ; Cleavelin, C.R. ; Schrufer, K. ; Georgakos, G. ; Schmitt-Landsiedel, D.
Author_Institution :
Infineon Technol., Munchen
Abstract :
We present an investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static noise margins (SNM) of 210 mV have been measured at IV VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.
Keywords :
SRAM chips; circuit tuning; field effect transistors; MuGFET; SNM; SRAM cells; multigate-FET technology; stability tuning; static noise margins; CMOS technology; Circuits; Inverters; MOS devices; Random access memory; Silicon; Stability; Tin; Variable structure systems; Writing;
Conference_Titel :
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1125-2
DOI :
10.1109/ESSCIRC.2007.4430325
