Title :
Noise and gain optimization technique for RF-integrated CMOS low noise amplifier
Author :
Nguyen, Trung-Kien ; Lee, Sang-Gug
Author_Institution :
Inf. & Commun. Univ., Daejeon, South Korea
Abstract :
In this paper, very simple and insightful sets of noise parameters expressions for power-constrained simultaneous noise and input matching CMOS LNA design technique are newly introduced. Based on the noise parameters expression, the design principle, advantages, and limitations are clearly explained. Additionally, this paper proposes a gain enhancement technique that is implemented by using simple positive feedback. The proposed LNA is optimized for 5 GHz WLAN applications based on 0.18 μm CMOS technology. Measurement results show power gain of 18 dB, NF of 1.5 dB, and IIP3 of -5 dBm while dissipates the DC current of 4 mA at supply voltage of 2.5 V.
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; integrated circuit noise; power amplifiers; power integrated circuits; radiofrequency amplifiers; radiofrequency integrated circuits; wireless LAN; 0.18 micron; 1.5 dB; 18 dB; 2.5 V; 4 mA; 5 GHz; CMOS LNA design; CMOS technology; RF-integrated CMOS low noise amplifier; WLAN applications; gain optimization; noise optimization; noise parameters; positive feedback; power gain; CMOS technology; Current measurement; Feedback; Gain measurement; Impedance matching; Low-noise amplifiers; Noise measurement; Power measurement; Voltage; Wireless LAN;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN :
0-7803-7749-4
DOI :
10.1109/EDSSC.2003.1283518
