DocumentCode :
2772308
Title :
A fail-safe ASIC for implantable neural stimulation
Author :
Liu, Xiao ; Demosthenous, Andreas
Author_Institution :
Univ. Coll. London, London
fYear :
2007
fDate :
11-13 Sept. 2007
Firstpage :
460
Lastpage :
463
Abstract :
We implemented a stimulator output stage that is failsafe without the need for off-chip blocking capacitors. Both the system architecture and details on the key circuits are described. The novel design employs high-frequency current-switching, a fully isolated bridge rectifier core, and AC-coupled discharging for the stimulation load. The prototype circuit was fabricated in a 1-mum silicon-on-insulator CMOS technology and operates from a power supply between the range of 5 V to 18 V, depending on the stimulation load and the stimulus current amplitude. Miniaturization of the entire stimulator output stage into a single fail-safe ASIC, is a major advance towards developing neural stimulators for multi-functional restoration after spinal cord injury.
Keywords :
CMOS integrated circuits; application specific integrated circuits; prosthetics; rectifiers; silicon-on-insulator; AC-coupled discharging; ASIC; bridge rectifier core; high-frequency current-switching; implantable neural stimulation; off-chip blocking capacitors; power supply; silicon-on-insulator CMOS technology; size 1 mum; stimulator output stage; voltage 5 V to 18 V; Application specific integrated circuits; Bridge circuits; CMOS technology; Capacitors; Isolation technology; Power supplies; Prototypes; Rectifiers; Silicon on insulator technology; Spinal cord injury;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location :
Munich
ISSN :
1930-8833
Print_ISBN :
978-1-4244-1125-2
Type :
conf
DOI :
10.1109/ESSCIRC.2007.4430342
Filename :
4430342
Link To Document :
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