Spectral PLL built-in self-test for integrated cellular transceivers

A built-in self test (BIST) solution for the on-chip spectral verification of a 4 GHz phase-locked loop (PLL) is presented. The PLL is embedded in an integrated cellular RF transceiver in a 130 nm CMOS technology. The BIST blocks enable the detection of catastrophic and many parametric faults by measuring the PLL frequency response and checking for spurious sidebands and excessive in-band phase noise without external test equipment. Multi-tone stimuli with a spurious-free dynamic range (SFDR) of 60 dB are generated on-chip, the PLL RF response is demodulated and digitized in an on-chip digital FM discriminator. Spectral analysis is performed using digital narrowband filtering, achieving an SFDR of 45 dB. The fully digital BIST blocks require a chip area of only 0.06 mm² and do not compromise the performance of the PLL itself.