Design of sub-50 nm ultrathin-body (UTB) SOI MOSFETs with raised S/D

This paper gives a general analysis on source/drain series resistance and parasitic capacitance of sub-50 nm UTB SOI MOSFETs with raised S/D through 2-D simulations. RC-delay tradeoff introduced from the use of UTB and raised S/D is studied and the result is presented. The combination with the use of low-K dielectric and sunk S/D structure are proposed to further reduce the serious and gate-to-drain capacitance while without degrading other device performance parameters. The advantages of the proposed structure is verified by 2D device simulation.