A 64-bit lookahead carry chain in Inverted-Domino logic

Here we present a novel 64-bit adder carry chain design implemented in Inverted-Domino (iDomino) logic that is an improved style over conventional Domino for better performance. In the proposed scheme capacitances at output node are reduced and foot transistor in Domino logic is absorbed into clock tree to increase circuit speed. A 64-bit lookahead carry chain is constructed and HSPICE simulation in 0.25 μm CMOS parameter shows that carry propagation can be done in less than 480 ps and a 20% speed enhancement over Domino is achieved.