Design methodology to achieve good testability of VLSI chips: An industrial perspective

Many of today´s very large scale integration (VLSI) chips are digital design that has hundreds of thousands to millions of transistors per chip. Testing of such large VLSI chips proves to be a challenge. One method of addressing this challenge is the introduction of design for test (DFT) features into the VLSI chips. This paper describes an efficient methodology of achieving good testability of VLSI chip using a combination of register transfer level (RTL) coding styles with full scan chain implementation and automatic test pattern generation (ATPG). This paper also describes the method of sharing of DFT pins associated with scan chain in order to reduce packaging cost due to DFT.