Design of SONOS memory transistor for terabit scale EEPROM

Author

Gritsenko, Vladimir A.

Author_Institution

Inst. of Semicond. Phys., Acad. of Sci., Novosibirsk, Russia

fYear

2003

fDate

16-18 Dec. 2003

Firstpage

345

Lastpage

348

Abstract

The approach for design of terabit scale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile FLASH memory, based on high-k dielectric is proposed. The comparison of simulated write/erase characteristics of SONOS with different oxides SiO₂, Al₂O₂ and ZrO₂ as a top dielectric was made. For the first time we demonstrate, that an application of high-k dielectrics allows to decrease the write/erase programming voltage amplitude or programming time from 1 ms to 10 μsec. The ZrO₂ suppresses parasitic electron injection from polysilicon gate. Also the design of SONOS memory based on high-k dielectrics is promising for terabit scale using hot carriers injection EEPROM and DRAM memory.

Keywords

alumina; dielectric materials; elemental semiconductors; flash memories; semiconductor device models; semiconductor-insulator boundaries; silicon; silicon compounds; zirconium compounds; 1 ms to 10 mus; Al₂O₂ dielectric materials; DRAM memory; Si-SiO₂-Si₃N₄-SiO₂-Si; ZrO₂ dielectric materials; dielectric materials application; memory transistor; parasitic electron injection; polysilicon gate; silicon oxide-nitride oxide-silicon nonvolatile flash memory; simulated write/erase properties; terabit scale EEPROM; write/erase programming voltage amplitude; Charge carrier processes; Dielectric constant; EPROM; Electron traps; High K dielectric materials; High-K gate dielectrics; Nonvolatile memory; Random access memory; SONOS devices; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2003 IEEE Conference on

Print_ISBN

0-7803-7749-4

Type

conf

DOI

10.1109/EDSSC.2003.1283546

Filename

1283546