Optimization of cascode CMOS low noise amplifier using inter-stage matching network

Author

Zhang, Cemin ; Huang, Daquan ; Lou, Dongwu

Author_Institution

Dept. of Electron. Eng., Zhejiang Univ., Hangzhou, China

fYear

2003

fDate

16-18 Dec. 2003

Firstpage

465

Lastpage

468

Abstract

The traditional cascode structure of CMOS low noise amplifier (LNA) is considered as a two-stage amplifier and inter-stage matching network is introduced accordingly. Deduction shows that a series inductor can be applied as the inter-stage matching network between the two stages. In the end, a 2-GHz CMOS low noise amplifier is designed as an example. Simulation results show that the noise and gain performances are improved evidently after the introduction of the series on-chip inductor.

Keywords

CMOS analogue integrated circuits; MOSFET; UHF amplifiers; cascade networks; inductors; integrated circuit modelling; integrated circuit noise; system-on-chip; 2 GHz; LNA; MOSFET; cascode CMOS low noise amplifier; interstage matching network; optimization; series inductor; series on-chip inductor; two-stage amplifier; CMOS technology; Circuit topology; Frequency; Inductors; Low-noise amplifiers; MOSFET circuits; Network topology; Noise figure; Parasitic capacitance; Power system reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2003 IEEE Conference on

Print_ISBN

0-7803-7749-4

Type

conf

DOI

10.1109/EDSSC.2003.1283574

Filename

1283574

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2773271