LiB: a cell layout generator

Author

Hsieh, Yung-Ching ; Hwang, Chi-Yi ; Lin, Youn-Long ; Hsu, Yu-Chin

Author_Institution

Electron. Res. & Service Organ., Ind. Technol. Res. Inst., Hsin-Chu, Taiwan

fYear

1990

fDate

24-28 Jun 1990

Firstpage

474

Lastpage

479

Abstract

An automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. In LiB, the intra-cell routing runs not only between PMOS and NMOS but also on diffusion islands as well as the two side regions (one between the PMOS diffusion and the power line, and the other between the NMOS diffusion and the ground line). Several heuristic algorithms are proposed to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems. Experimental results are presented to show the capability of LiB

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit layout CAD; CMOS ASIC design; LiB; NMOS; PMOS; SPICE format; automatic layout generation system; cell layout generator; chain placement; chaining; folding; heuristic algorithms; library cells; net assignment; pairing; routing; symbolic layout; transistor-clustering; transistor-level circuit schematic; Application specific integrated circuits; CMOS technology; Clustering algorithms; Computer science; Electronics industry; Industrial electronics; Libraries; MOS devices; Routing; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114902

Filename

114902