Static CMOS implementation of Logarithmic Skip Adder

Circuit design of 32-bit Logarithmic Skip Adder (LSA) is introduced to implement high performance, low power addition. At architecture level, ELM carry look ahead adder is included into blocks of carry skip adder and the hybrid architecture of LSA costs 30% less hardware than ELM. At circuit level carry-incorporating structure to include the primary carry input in carry chain and and-xor structure to implement final sum logic are designed. Circuit simulation using spectre simulator are presented and compared with recent literatures´. For 2.5 v, 0.25 μm process, critical delay of 0.8 ns, power dissipation of 5.2 mw at 100 MHz is simulated.