A clustering based area I/O planning for flip-chip technology

The complexity of nanometer SoC design requires the codesign and development of circuit design and packaging technology to enable a successful \´total integrated solution\´. In this paper we introduce a new area I/O algorithm for the recent flip-chip packaging technology. The algorithm combines a clustering technique with area I/O planning algorithm to avoid iterations during "placement and area I/O pad assignment". Experiment results show that the total interconnect length (including both on-chip and off-chip parts) and delay are reduced by 10-15% comparing with traditional algorithms.