Thermal design for flip chip on board in natural convection

In this paper, thermal features of flip chip on FR4 boards with different control variables are discussed. The control variables include die size, board construction, bump pattern, underfill material and inclusion of a heat spreader. Thermal paths are analyzed to determine the heat dissipation mechanism. Due to the decreased package surface for direct flip chip on board, the junction to ambient thermal resistance is significantly dominated by the carrier board, differing with values for conventional large size packages. Therefore, apart from the thermal resistance value acquired from standard measurements, more package performance information is needed for the system designer. Accordingly, the maximum device junction temperature and power dissipation limit of the package are chosen to establish package thermal design guidelines. The three-resistor network model can determine the solution satisfying the junction and board temperature constraints. This study projects the thermal performance limits of flip chip. An experimentally validated computational fluid dynamics model is used for the flip chip on board thermal design. The die size, board construction and heat spreader inclusion are vital performance factors. As the junction-to-board resistance is small, the board temperature constraint decides the allowable flip chip power dissipation. With fixed die size in applications, an enhancement applying a heat spreader is essential when using a low conductivity carrier board. The methodology in this study can be used for other package design tasks, especially for future small packages.