Estimating phase-locked loop jitter due to substrate coupling: a cyclostationary approach

Author

Chan, Henry H Y ; Zilic, Zeljko

Author_Institution

Dept. of ECE, McGill Univ., Montreal, Que., Canada

fYear

2004

fDate

2004

Firstpage

309

Lastpage

314

Abstract

On-chip phase-locked loops (PLLs) are critical components for clock generation and recovery in high-speed communication and data processing systems. The presence of partially-correlated substrate noise presents a new challenge to predicting PLL jitter. We propose a model that describes the substrate noise-to-jitter transfer characteristics for CMOS ring oscillator-based PLLs on epitaxial substrates. The proposed model is verified against jitter simulations.

Keywords

CMOS integrated circuits; coupled circuits; integrated circuit modelling; integrated circuit noise; jitter; phase locked loops; voltage-controlled oscillators; CMOS ring oscillator; PLL jitter estimation; clock generation; clock recovery; cyclostationary method; data processing systems; epitaxial substrate; high-speed communication systems; on-chip phase-locked loops; partially-correlated substrate noise; substrate coupling; substrate noise-to-jitter transfer characteristics; Conductivity; Delay; Jitter; Noise generators; Phase estimation; Phase locked loops; Phase noise; Semiconductor process modeling; Substrates; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2004. Proceedings. 5th International Symposium on

Print_ISBN

0-7695-2093-6

Type

conf

DOI

10.1109/ISQED.2004.1283691

Filename

1283691