Balanced microprocessor design keeps performance peaked

The factors that determine a CPU´s (central processing unit´s) performance are presented, and the design solutions featured by the NS32532 microprocessor are described. As the CPU´s operating frequency increases, the decisions on the CPU´s pipeline configuration and on which support mechanisms to integrate on chip become crucial for the CPU´s sustained performance in a system. In order to sustain an 8 to 10 MIPS average performance at 30 MHz in a realistic system, the NS32532 microprocessor was designed as a balanced machine. It integrates an MMU (memory management unit) and twin caches on chip, in order to supply instructions and operands at the speed requested by the fast instruction execution pipeline. Pipeline mechanisms like operand prefetch and branch prediction also help maximize the system performance. Data dependencies are solved in NS32532 by hardware, in order to be able to run Series 3200 code without any modification and get a very significant performance boost. A carefully designed bus interface gives full support to high-performance system design. In lower cost systems wait states are necessary, but their penalty is cushioned by the lower performance degradation per wait state (only 3 to 5% per wait state, compared to about 20% for other microprocessors)