DocumentCode :
2774692
Title :
Analytical dynamic time delay model of strongly coupled RLC interconnect lines dependent on switching
Author :
Shin, Seongkyun ; Eo, Yungseon ; Eisenstadt, William R. ; Shim, Jongin
Author_Institution :
Dept. of Electr. & Comput. Eng., Hanyang Univ., Kyungki-Do, South Korea
fYear :
2004
fDate :
2004
Firstpage :
337
Lastpage :
342
Abstract :
In today´s UDSM(ultra-deep-sub-micron)-process-technology-based ICs, dynamic delay variations of strongly coupled lines (due to neighboring net switching activity) make static timing analysis problematic. In this paper, new analytical timing models for RLC coupled lines are presented and their accuracy is verified. Coupled interconnect lines are decoupled into an effective single line model by using effective capacitances and effective inductances corresponding to switching activity. Their signal transient waveforms of the effective single line models are determined by exploiting the TWA (Traveling-wave-based Waveform Approximation) technique. This is followed by single line analytical timing model development. It is shown that the models have excellent agreement with SPICE simulations for various circuit performance parameters such as line pitch, line length, driver/receiver size, IMD-thickness, and aspect ratio.
Keywords :
RLC circuits; SPICE; VLSI; capacitance; crosstalk; delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; timing; transmission line theory; waveform analysis; SPICE simulations; VLSI circuit designs; analytical dynamic time delay model; aspect ratio; dynamic delay variations; effective capacitances; effective inductances; effective single line model; line length; line pitch; neighboring net switching activity; signal transient waveforms; static timing analysis; strongly coupled RLC interconnect lines; switching dependence; transmission line model parameters; traveling-wave-based waveform approximation; ultra-deep-submicron process technology; Analytical models; Capacitance; Circuit optimization; Circuit simulation; Coupled mode analysis; Delay effects; Driver circuits; Integrated circuit interconnections; SPICE; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
Print_ISBN :
0-7695-2093-6
Type :
conf
DOI :
10.1109/ISQED.2004.1283697
Filename :
1283697
Link To Document :
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