MID: a Novel Coherency Protocol in Chip Multiprocessor

Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors[1]. The shared on-chip cache will cause data inconsistent. This paper proposes a specification methodology that documents and specifies a cache coherence protocol in chip multi-processor. This protocol contains five states and we use three state bits to describe these states. In this protocol, we take full advantage of the rapid data exchanging between the processors in CMP. All the processors¿ level one caches (L1D) link on a ring bus. Every processor can access all L1D¿s Tag simultaneously to judge whether or not the memory access hit other L1Ds. We then take a detailed compare between this protocol and MESI protocol. Simulation results show that the MID protocol has an improvement of up to 30% comparing with MESI protocol.