A BiCMOS digital filter for HDTV

Developments in the consumer electronics and telecommunications industry demand better performance integrated circuits with mixed analogue and digital (A-D) functions, suggesting a combination bipolar and CMOS technology. The primary aim for designing this high speed cascadable 3-tap FIR filter is to demonstrate the ability of BiCMOS technology to accommodate the design of sub elements which must exist in a high speed, high performance digital signal processing (DSP) environment such as high definition television (HDTV) applications. In addition to dealing with the filter architecture, this contribution describes how in particular a combined bipolar-CMOS approach resulted in a satisfactory clocking scheme and output buffers