Abstract :
It is well known that feature sizes of VLSI/ASIC processes are continually shrinking. The requirement for similar shrinkage of design lead times suggests that any changes to technology design rules can have a catastrophic effect upon time-to-market if design methods do not anticipate or accommodate this shrinkage. Many ASIC foundries offer an `umbrella´ set of design rules which are scalable by a global `lambda´ factor, however, this approach cannot exploit all of the minimum features of all the processes; thus an area penalty is paid in each design. A different approach is to use design rule based compilation and compaction. Here, object based cells and blocks are compiled using a parameterised technology file. User directed incremental compaction is built into the cells based upon these design rule parameters, which enable very high densities to be achieved. If a process rule changes during a design, then the relevant parameter is changed in the technology file and the cell or block is recompiled. The author investigates the contrasts between object based (procedural) layout, and the more traditional umbrella approach, highlighting where advances in database technology can be exploited to support the ever increasing requirement for process portable libraries
