Development of Flip Chip Die Bump Temperature Measurement Methodology Using a Computational Fluid Dynamics (CFD) Tool

Die bump temperature become engineering challenge because both thermal design power (TDP) and die bump electrical current increased with flip chip functionality. Die bumps with smaller geometry experienced higher heat flux than silicon die. Thus, an accurate modeling and empirical methodology are needed in order to understand die bump temperature measurement accuracy and self-heating characteristic. This paper outlines and demonstrates the advantages of applying numerical modeling in chipset die bump temperature measurement methodology development and use conditions evaluation. Two types of die bump temperature measurement designs have been evaluated during early stage of design cycle, these included single and multiple die bump structure designs. JEDEC test standard in thetas-JA (JESD51-2, junction to still air thermal resistance) has been used as design validation and follow by typical desktop computer use conditions evaluation. In an effort to develop comprehensive understanding of die bump self-heating characteristic, a commercial computational fluid dynamics (CFD) engineering tool has been employed. Both global and local CFD modeling analysis suggested multiple die bump temperature measurement design provided more accurate result than single die bump design. Silicon trace self-heating in single die bump design has over estimated the die bump temperature during actual use conditions. In addition, die bump self-heating characteristic is impacted by non-uniform heating effect, current density, TDP and different die bump material options. Thus, an accurate die bump temperature measurement methodology has been developed through both numerical and empirical validation.