IC immunity modeling process validation using on-chip measurements

Author

Ben Dhia, S. ; Boyer, A. ; Vrignon, B. ; Deobarro, M.

Author_Institution

Electron. Dept., Univ. of Toulouse, Toulouse, France

fYear

2011

fDate

27-30 March 2011

Firstpage

1

Lastpage

6

Abstract

Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process.

Keywords

flow simulation; integrated circuit design; integrated circuit modelling; integrated circuit testing; radiofrequency interference; IC immunity modeling process validation; integrated circuit immunity modeling process validation; on-chip measurement; on-chip voltage sensor; radiofrequency interference propagation; standard immunity test; Integrated circuit modeling; Noise; Power supplies; Predictive models; Semiconductor device measurement; System-on-a-chip; Integrated circuit; immunity modelling; on-chip measurement; power supply network modelling;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop (LATW), 2011 12th Latin American

Conference_Location

Porto de Galinhas

Print_ISBN

978-1-4577-1489-4

Type

conf

DOI

10.1109/LATW.2011.5985912

Filename

5985912