DocumentCode :
2777248
Title :
Stress Studies to Optimize the FCBGA Bumping Structure
Author :
Tzeng, Yuan Lin ; Lai, Jeng Yuan ; Wang, Yu Po ; Hsiao, C.S.
Author_Institution :
Siliconware Precision Ind. Co. Ltd., Taichung
fYear :
2006
fDate :
11-14 Dec. 2006
Firstpage :
1
Lastpage :
5
Abstract :
Flip chip ball grid array (FCBGA) was developed to meet the requirements of more functionality, excellent electrical performance, high input/output (I/O) density and high speed in semiconductor device market. In the past experience, the frequent coming challenges were bump fatigue crack and low-k chip delamination caused by Coefficient of Thermal Expansion (CTE) mismatch between chip and substrate during the reliability tests. In order to elevate the resistance of bump crack and low-k delamination in FCBGA, selecting suitable bumping structure is the one of key solutions to ensure the FCBGA package success. The studies in this paper were employed finite element method (FEM) modeling and mainly covered the detail bumping structure analyses in terms of bump and low-k stresses. The bumping structures were considered with both single and dual passivation and polyimide layers to protect bumps from thermal stress destroy and they were mentioned to include four different structures in this paper, such as single passivation (single PSV), single passivation-polyimide (single PSV-PI), dual passivation (dual PSV) and dual passivation-polyimide (dual PSV-PI). Moreover, the geometry dimension combinations of copper pad size, passivation open, polyimide open and thickness were also discussed in this paper to identify the optimal dimension design with lower stress risk. Further, the under-bump metallization (UBM) sizes were also considered with different substrate solder mask opening (SMO) sizes to compare the bump stress level. In the conclusion of this stress analyses, the paper derived some bumping structure design guidelines. Dual passivation-polyimide performs the smallest bump and die surface stresses among the four different bumping structures. The optimal dimension combinations of polyimide opening and thickness, passivation opening and copper pad size were recommended to gain lower stress for bump and low-k. Finally the study also identified the optimum ratio as 1:1 betwe- en UBM and SMO sizes to acquire the minimum bump stress.
Keywords :
ball grid arrays; crack-edge stress field analysis; finite element analysis; flip-chip devices; passivation; reliability; bump fatigue crack; bump stress level; bumping structure design guideline; die surface stress; dual passivation-polyimide; finite element method modeling; flip chip ball grid array bumping structure; geometry dimension combination; low-k chip delamination; minimum bump stress; polyimide layer; reliability test; semiconductor device market; single passivation-polyimide; stress analysis; substrate solder mask opening; thermal expansion coefficient mismatch; under-bump metallization; Copper; Delamination; Electronics packaging; Fatigue; Flip chip; Passivation; Polyimides; Semiconductor devices; Substrates; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on
Conference_Location :
Kowloon
Print_ISBN :
978-1-4244-0834-4
Electronic_ISBN :
978-1-4244-0834-4
Type :
conf
DOI :
10.1109/EMAP.2006.4430615
Filename :
4430615
Link To Document :
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