DocumentCode :
2777355
Title :
Electroless Plating Ni-based Barrier Layers for 3D Interconnection
Author :
Jian Cai ; Feng, Guoqiang ; Yang, Zhigang ; Wang, Shuidi ; Songliang Jia
Author_Institution :
Tsinghua Univ., Tsinghua
fYear :
2006
fDate :
11-14 Dec. 2006
Firstpage :
1
Lastpage :
6
Abstract :
Cu is the key material for both on-chip and inter-chip interconnections. It is the major interconnect material in packaging level, especially in through wafer electrical interconnection (TWEI). Barrier layer is necessary as Cu is easy to diffuse into Si, SiO2 and other dielectrics. Comparing with traditional Ta and Ti based barrier layers, electroless plating NiMoP film has many advantages, such as seedless, low cost, lower resistivity, etc. Electroless plating NiMoP was investigated on SiO2/Si. The plating solution was made up in house. Nickel sulfate and sodium molybdate were the sources of nickel and molybdenum. The effects of [MoO4 2-]/[Ni2+] on the deposition rate of NiMoP and the film composition, electricity property, surface morphology & crystal structure were investigated. The deposition rate of NiMoP would be stable when the ratio of [MoO4 2-]/[Ni2+] is higher than 0.08. The atom percentage of Mo in NiMoP film increases with the increasing of [MoO4 2-]/[Ni2+]initially and then reaches a saturation amount at about 10 at%, while the concentration of P decreases with the increasing [MoO4 2-]/[Ni2+]. The resistivity of NiMoP film can be as low as 70.2 muOmegacm. The optimized deposition condition for a low resistivity NiMoP barrier is with the pH value of 9.0-10.0, plating temperature in the range of 85-90degC and [MoO4 2-]/[Ni2+]of around 0.043. With Auger analysis, the deposited NiMoP film can be the effective diffusion barrier layers after 400degC annealing. A demonstration of 3D interconnection with electroless NiMoP barrier layer has been fabricated.
Keywords :
copper; crystal structure; diffusion barriers; electric properties; electrodeposition; electroless deposition; integrated circuit interconnections; surface morphology; 3D interconnection; Auger analysis; NiMoP-Cu-SiO2-Si; crystal structure; deposition rate; diffusion barrier layers; electricity property; electroless plating; film composition; inter-chip interconnections; interconnect material; on-chip interconnection; optimized deposition condition; surface morphology; temperature 400 degC; through wafer electrical interconnection; Adhesives; Chemical vapor deposition; Conductivity; Costs; Dielectric materials; Nickel; Packaging; Power system interconnection; Sensor arrays; Silicon; 3D Interconnection; Barrier Layer; Electroless Plating; NiMoP;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on
Conference_Location :
Kowloon
Print_ISBN :
978-1-4244-0834-4
Electronic_ISBN :
978-1-4244-0834-4
Type :
conf
DOI :
10.1109/EMAP.2006.4430621
Filename :
4430621
Link To Document :
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