• DocumentCode
    2777930
  • Title

    Building-in Reliability for VLSI

  • Author

    Xin-yao, Zou ; Ruo-he, Yao

  • Author_Institution
    South China Univ. of Technol., Guangzhou
  • fYear
    2006
  • fDate
    11-14 Dec. 2006
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Building-in reliability (BIR) was introduced in the early of 1990´s. It is a methodology to manufacture highly reliable IC by minimizing and eliminating the sources of product unreliability in the beginning of a new product process. The characteristic of integrated reliability about BIR diffuses the responsibility for reliability into the whole team, including not only the process/ reliability/ characterization engineers, but also the applied research engineers and the customers who use integrated circuits. It´s well known that the quality and reliability are defined by the customer, not by the manufacturers. So the customer´s role in BIR is very important, especially the responsibilities of establishing good communications with the manufacturer and returning all failures to the manufacturer. The quality function deployment (QFD) and qualified manufacturer´s list (QML) can help the customer take his responsibilities. In addition, nowadays little progress has been made in charactering the reliability of the future high reliability of VLSI after using the BIR approach. Small-sample statistical theory, especially for support vector machines (SVM) will be attempted to assess the reliability of VLSI.
  • Keywords
    VLSI; integrated circuit design; integrated circuit manufacture; integrated circuit reliability; quality function deployment; statistical analysis; support vector machines; VLSI; building-in reliability; customer responsibilities; highly reliable IC manufacturing; qualified manufacturer´s list; quality function deployment; small-sample statistical theory; support vector machines; Integrated circuit reliability; Life estimation; Lifetime estimation; Manufacturing processes; Quality function deployment; Reliability engineering; Reliability theory; Semiconductor device manufacture; Support vector machines; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on
  • Conference_Location
    Kowloon
  • Print_ISBN
    978-1-4244-0834-4
  • Electronic_ISBN
    978-1-4244-0834-4
  • Type

    conf

  • DOI
    10.1109/EMAP.2006.4430654
  • Filename
    4430654