DocumentCode :
2778187
Title :
Substrate Design & Process Optimization of LGA (BT-based) Package
Author :
Chew, Carrie ; Chip King Tan
Author_Institution :
Fairchild Semicond. (Malaysia) Sdn. Bhd., Penang
fYear :
2006
fDate :
11-14 Dec. 2006
Firstpage :
1
Lastpage :
10
Abstract :
With the trends moving towards smaller packaging technologies, land grid array (LGA) is rapidly becoming the package of choice. BT (bismaleimide triazine) substrate is being used due to its excellent electrical insulation, low CTE and high Tg. Optimized substrate design is essential in ensuring reliable package performance at field. Finite element analysis was performed on two different substrate designs in selecting the most optimized design with the lowest stress level and best performance in assembly process. Process optimization is another important aspect in attaining a robust package. Characterization of two-step wafer sawing has shown to be helpful in minimizing back side chipping for a 6 mils die laminated with non-conductive die attach film. With the use of DAF, die attach is necessary to be done at elevated temperature. Optimized setting of bond force, temperature and cure profile has shown to be crucial in achieving desirable BLT, minimum bleed, void and out-gassing from the adhesive. Wire bond temperature has been demonstrated to be critical to bonding quality with the tradeoff of DAF out-gassing at high temperature. Heater block design coupled with the right setting of pre-heat delay and temperature are necessary in achieving sufficient ball shear strength for BSOB. Plasma cleaning is another area of focus where magazine design, plasma loading capacity and the parameters were shown to be the important factors in ensuring effective cleaning.
Keywords :
assembling; ball grid arrays; process design; substrates; assembly process; ball shear strength; bismaleimide triazine substrate; bond force; electrical insulation; finite element analysis; heater block design; land grid array; optimized substrate design; packaging technology; plasma cleaning; plasma loading capacity; process optimization; stress level; wire bond temperature; Bonding; Cleaning; Design optimization; Dielectrics and electrical insulation; Microassembly; Packaging; Plasma applications; Plasma temperature; Process design; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on
Conference_Location :
Kowloon
Print_ISBN :
978-1-4244-0834-4
Electronic_ISBN :
978-1-4244-0834-4
Type :
conf
DOI :
10.1109/EMAP.2006.4430670
Filename :
4430670
Link To Document :
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