Logical circuit gate sizing using PSO guided by Logical Effort — An examination of the 4-stage half adder circuit

Automated Complementary Metal Oxide Semiconductor (CMOS) logic circuit design leads to the reduction in costs associated with manpower and manufacturing time. Conventional methods use repetitive manual testing guided by Logical Effort (LE). LE provides an easy way to compare and select circuit topologies, choose the best number of stages for path and estimate path delay. In this paper, we propose the Particle Swarm Optimization (PSO) algorithm as a method to automate the process of CMOS circuit design by approaching the design process as an optimization problem. In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, and its fitness is guided by the LE method. Various parameters, such as swarm size and iterations were tested under different initialization conditions to verify PSO´s performance on a 4-stage half-adder circuit. Results have indicated that the PSO algorithm was an effective method to apply to the circuit design problem, with high convergence rates observed.