DocumentCode
2778248
Title
Chortle: a technology mapping program for lookup table-based field programmable gate arrays
Author
Francis, Robert J. ; Rose, Jonathan ; Chung, Kevin
Author_Institution
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
fYear
1990
fDate
24-28 Jun 1990
Firstpage
613
Lastpage
619
Abstract
An algorithm is described for technology mapping of combinational logic into field programmable gate arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle, uses the fact that a K -input lookup table can implement any Boolean function of K inputs and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparison with the MIS II technology mapper, on MCNC-89 LOGIC Synthesis benchmarks Chortle achieves superior results in significantly less time
Keywords
Boolean functions; circuit layout CAD; combinatorial circuits; logic CAD; logic arrays; table lookup; Boolean function; Chortle; K-input lookup table; combinational logic; fanout-free trees; field programmable gate arrays; logic functions; lookup table memories; technology mapping; Boolean functions; Field programmable gate arrays; Libraries; Logic design; Logic devices; Logic functions; Network synthesis; Programmable logic arrays; Table lookup; Vegetation mapping;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location
Orlando, FL
ISSN
0738-100X
Print_ISBN
0-89791-363-9
Type
conf
DOI
10.1109/DAC.1990.114927
Filename
114927
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