A 45 Mb/s high speed performance monitoring chip for digital transmission system

Author

Wu Ji Tsu ; Been-Hwang, Liao ; Chen-Shiung-Chung ; Chi-Chou, Lin ; Wu-Jhy, Chiu ; Chi-Yuan, Wu

fYear

1989

fDate

17-19 May 1989

Firstpage

380

Lastpage

384

Abstract

A 45-Mb/s DS-3 performance monitoring chip, the PM45M, has been designed and simulated using a 1.5-μm-channel-length BiMOS process with 6000 equivalent gates. A discussion is presented of special features, function architecture, design strategies and tradeoffs involved at the various stages in the design of the VLSI (very-large-scale integration) chip. With a full complement of monitoring features and sophisticated performance parameters, the chip is very flexible and easy to use

Keywords

BIMOS integrated circuits; VLSI; data communication systems; digital communication systems; digital integrated circuits; monitoring; 1.5 micron; 45 Mbit/s; BiMOS process; DS-3 performance monitoring; PM45M; VLSI; channel length; design strategies; digital transmission system; function architecture; high speed performance monitoring chip; tradeoffs; Availability; Bit error rate; Buffer storage; Chip scale packaging; Circuit testing; Condition monitoring; Design methodology; Laboratories; Remote monitoring; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68650

Filename

68650