Modeling the behaviour of the sub-micron MOS transistors in mixed-signal integrated circuits

Recent mixed-signal circuits designed in deep sub-micron technologies uses 5-7 interconnection layers. The distributed capacitance between these layers, the increased resistance of the current path, due to the high W/L ratio, and the inductances of the terminals act as complex loads for the MOS transistors operated at small signal. This paper studies the behaviour of the sub-micron MOS transistors with mixed (resistive/inductive) loads and points out several methods for improving the circuit parameters. The aspect of the distributed resistance and capacitance of the interconnection lines between the circuit and the load is also discussed. The wire sizing problem, which for a great part of the circuit designers is based on the DC value, is analysed from a new point of view: signal propagation