Low-Input High-Output Synchronous Rectification Boost DC-DC Simulation Based on MOSFET Model Scaling Down to 22nm

Aiming at tree electricity generation key technology, an ideal synchronous rectification structure boost converter is focused on training important variables in sequence of (1) output load R=20O, (2) C and L, (3) especially switch-on RN and RP, (4) W/L, and (5) area of MOSFET. The simulation results suggest that (1) there is a CRL (conversion ratio limit) effect, (2) the conversion ratio is not only effected by duty ratio, but also adversely proportional to R_N; (3) under the same W/L, only the 130nm, 90nm, and 65nm technology nodes may be the best choices, (4) for purposed circuit, the 65nm technology node may fit with low load resistance and high CRL. Compared to output power 100uW reported, CRL in output 50mW with a 20Ω load resistor had been predicted by 65nm node MOSFET model libraries.