MOS functional device with increased transconductance

In sub-micron technologies, reducing the electronic devices dimensions under 100nm creates strong advantages, such as increased density of the devices and higher working frequency. Scaling down the structures has some drawbacks. The most important one, concerning the signal amplifiers, is the very small transconductance value when operating the MOS transistor at subthreshold conditions[1]. Increasing the width of the device is not a suitable solution for a higher transconductance because it implies large silicon areas and lower frequency. In this paper a new MOS functional device is presented. This device is SPICE simulated and it has a I_D ~ V_GS ³ dependence replacing the classical quadratic I_D ~ V_GS ² solution of the MOS transistor in saturation regime. This new device also introduces a new point of view for the "super- slope" MOS devices concept