DocumentCode :
277943
Title :
Test strategy planning environments for VLSI systems
Author :
Dear, I.D. ; Dislis, C. ; Ambler, A.P.
Author_Institution :
Dept. of Electr. & Electron. Eng., Brunel Univ., Uxbridge, UK
fYear :
1991
fDate :
33269
Firstpage :
42401
Lastpage :
42407
Abstract :
Some of the approaches available for test strategy planning that computer aided design (CAD) systems offer are outlined. The authors discuss the novel approach adopted by Brunel University to enable testability improvements to a design to be considered in financial terms. This work was initially funded as part of the ALVEY CAD042 program and subsequently under the EVEREST ESPRIT contract. The integration of the resulting system, ECOTEST into a CAD system is also described
Keywords :
VLSI; circuit CAD; circuit reliability; economics; testing; ALVEY CAD042 program; CAD system; ECOTEST; EVEREST ESPRIT contract; VLSI systems; computer aided design; financial terms; planning environments; test strategy planning; testability improvements;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Design Management Environments in CAD, IEE Colloquium on
Conference_Location :
London
Type :
conf
Filename :
180958
Link To Document :
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