Packaging challenges in the design of a 800 Mbps source-synchronous simultaneous bi-directional parallel interface

This paper describes the packaging issues, challenges and design solutions for a high-speed, point-to-point, low latency, high-bandwidth, simultaneous bi-directional interface used for board-to-board and box-to-box coupling of the system bus and/or I/O bus. Major design issues such as attenuation, crosstalk, delay skew, impedance control and inter-symbol interference for long and parallel external interconnection are discussed, along with the timing and jitter budget allocation. Design guidelines are provided for a 3.2 MB/sec physical interface using two bytes of simultaneous bi-directional data operating at 400 MHz double data transfer rates (DDR)