• DocumentCode
    2779601
  • Title

    Enhanced LVDS for signaling on the RapidIOTM interconnect architecture

  • Author

    Young, Brian

  • Author_Institution
    Somerset Design Center, Motorola Inc., Austin, TX, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    17
  • Lastpage
    20
  • Abstract
    Low voltage differential signaling (LVDS) is an established signaling standard for data rates up to about 600 Mb/s. The RapidIO interconnect architecture is an emerging protocol that uses LVDS for unidirectional point-to-point communication between two components on a board or in a backplane environment. The simulated performance and design trade-offs of source-terminated LVDS are shown for enhanced data rates of over 2 Gb/s
  • Keywords
    ball grid arrays; ceramic packaging; circuit simulation; interconnections; protocols; signalling; system buses; 2 Gbit/s; 600 Mbit/s; CBGA package; LVDS; RapidIO interconnect architecture; backplane environment; board components; data rates; design trade-offs; enhanced data rates; low voltage differential signaling; protocol; signaling; signaling standard; simulated performance; source-terminated LVDS; unidirectional point-to-point communication; Acoustic reflection; Circuit simulation; Connectors; Driver circuits; FETs; Integrated circuit interconnections; Packaging; Power dissipation; Resistors; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.
  • Conference_Location
    Scottsdale, AZ
  • Print_ISBN
    0-7803-6450-3
  • Type

    conf

  • DOI
    10.1109/EPEP.2000.895483
  • Filename
    895483
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2779601