Design, modeling and simulation methodology for PCI-X subsystems

Author

Cases, M. ; Pham, N.

Author_Institution

IBM Corp., Austin, TX, USA

fYear

2000

fDate

2000

Firstpage

33

Lastpage

36

Abstract

This paper describes an electrical design, modeling and simulation methodology for high-speed I/O subsystems utilizing an extension of the peripheral component interface specifications (PCI-X). Actual system configurations and timing specifications are used to describe the design methodology, and to optimize the timing equations for the system level interconnects. The timing budget and noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated critical design parameters including hot plug requirements

Keywords

design engineering; digital simulation; interconnections; noise; optimisation; peripheral interfaces; timing; PCI-X; PCI-X subsystems; critical design parameters; design; design methodology; electrical design; high-speed I/O subsystems; hot plug requirements; modeling; noise margin allocation; optimization equations; peripheral component interface specifications extension; simulation methodology; system configurations; system level interconnects; timing budget; timing equations optimization; timing specifications; Bandwidth; Clocks; Crosstalk; Delay effects; Design methodology; Design optimization; Equations; Frequency; Propagation delay; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.

Conference_Location

Scottsdale, AZ

Print_ISBN

0-7803-6450-3

Type

conf

DOI

10.1109/EPEP.2000.895487

Filename

895487