DocumentCode :
2780029
Title :
Efficiency of low-power design techniques in multi-gate FET CMOS circuits
Author :
Pacha, C. ; von Arnim, K. ; Bauer, F. ; Schulz, T. ; Xiong, W. ; San, K.T. ; Marshall, A. ; Baumann, T. ; Cleavelin, C.-R. ; Schruefer, K. ; Berthold, J.
Author_Institution :
Infineon Technol., Munich
fYear :
2007
fDate :
11-13 Sept. 2007
Firstpage :
111
Lastpage :
114
Abstract :
Energy dissipation, performance, and voltage scaling of multi-gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.
Keywords :
MOSFET circuits; integrated circuit design; integrated circuit testing; low-power electronics; energy dissipation; frequency 370 MHz to 500 MHz; low-power design techniques; multigate FET CMOS circuits; product-representative test circuits; short-channel effect control; voltage 1.2 V; voltage scaling; CMOS technology; Circuit analysis; Circuit testing; Clocks; Energy dissipation; FETs; Frequency; Performance analysis; Scalability; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European
Conference_Location :
Munich
ISSN :
1930-8876
Print_ISBN :
978-1-4244-1123-8
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2007.4430891
Filename :
4430891
Link To Document :
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