Thermal resistance reduction in power MOSFETs integrated in a 65nm SOI technology

The static and dynamic analysis of the thermal resistance (R_TH) in 65 nm SOI DriftMOS power devices is presented in this work. Experiment and numerical simulation are both used to compare DriftMOS devices integrated in 65 nm and 130 nm SOI technologies. Important R_THmiddot drop (between 40% and 60%) is found by experiment at 65 nm technology, basically due to the thinner buried oxide (BOX) layer. However, numerical simulation reveals a lower R_THmiddot reduction in the hottest point of the SOI active layer, shifted down about 15%. Furthermore, the R_THmiddot dependence with device geometrical parameters is investigated and the different layer contributions to the global thermal resistance are identified.