Data acquisition and handling for the simulation of ASIC by utilizing SW/HW co-design methodology

Author

Muhammad, Kamran ; Shi, Feng ; Suhail, Aftab Qureshi

fYear

2005

fDate

17-18 Sept. 2005

Firstpage

283

Lastpage

288

Abstract

ASIC design in the area of image processing needs large input output pixel data to be dealt with. The input image data is generated from input image which creates problems during ASIC simulation process. Manual manipulation of such a large data is not feasible while developing test bench for ASIC testing and simulation. This paper presents the methodology to highlight the approach of co-design to be used in such applications. Moreover, a revised scalable compression algorithm is proposed based on discrete cosine transform to improve ASIC behavioral architecture.

Keywords

application specific integrated circuits; data acquisition; data handling; discrete cosine transforms; field programmable gate arrays; hardware-software codesign; image processing; ASIC behavioral architecture; ASIC simulation process; FPGA; codesign methodology; data acquisition; data handling; discrete cosine transform; image processing; scalable compression algorithm; Application specific integrated circuits; Data acquisition; Design engineering; Discrete cosine transforms; Discrete wavelet transforms; Hardware; Image coding; Streaming media; Testing; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Technologies, 2005. Proceedings of the IEEE Symposium on

Print_ISBN

0-7803-9247-7

Type

conf

DOI

10.1109/ICET.2005.1558895

Filename

1558895