Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

Author

Kim, Yong Soo ; Lim, Kwan-Yong ; Sung, Min-Gyu ; Kim, Soo-Hyun ; Yang, Hong-Seon ; Cho, Heung-Jae ; Jang, Se-Aug ; Oh, Jae-Geun ; Kim, Kwangok ; Jung, Young-Kyun ; Jung, Tae-Woo ; Kim, Choon-Hwan ; Lee, Doek-Won ; Kim, Won ; Kim, Young-Hoon ; Choi, Kang-S

Author_Institution

Hynix Semicond. Inc., Kyoungki-do

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

259

Lastpage

262

Abstract

We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B₂H₆-based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.

Keywords

DRAM chips; chemical vapour deposition; diffusion barriers; titanium; tungsten compounds; Ti-WN; chemical vapor deposition; diffusion barrier; high density memory devices; high speed memroy devices; improved transistor performances; low resistive tungsten dual polymetal gate process; signal delay characteristics; Annealing; Capacitance measurement; Chemical vapor deposition; Current measurement; Delay; Electric resistance; Electrical resistance measurement; Hydrogen; Random access memory; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European

Conference_Location

Munich

ISSN

1930-8876

Print_ISBN

978-1-4244-1123-8

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2007.4430927

Filename

4430927