Investigations on fault tolerant clock synchronization within a powerline communication structure

In modern powerline communication (PLC) systems, clock synchronization is a very crucial issue. First the PLC network itself needs synchronized clocks for controlling the time-sliced communication, second also backbone networks and access points have to be coordinated in a fault tolerant fashion in order to ensure fast log-on and log-off of nodes travelling from one access point to another. This paper presents an approach to synchronize clocks in such a system with special support of IEEE 1588 compliant master groups. In the lower levels of the hierarchical system, attention has to be paid to the special behaviour of the PLC network. To tackle this, a methodology to use the IEEE 1588 format and protocol stack is presented. Finally measurements of the behaviour of the clock quality are analysed for both, Ethernet and PLC, by evaluating the Allan deviation