DocumentCode
2781214
Title
MISER: an integrated three layer gridless channel router and compacter
Author
Gidwani, Roshan ; Sherwani, Naveed A.
Author_Institution
Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
fYear
1990
fDate
24-28 Jun 1990
Firstpage
698
Lastpage
703
Abstract
Presented is a new gridless, three-layer channel router (MISER) based on an integrated approach to routing and compaction in VLSI design. MISER partitions the input net-list into several sub-net-lists called levels and forms a level-graph. This level-graph is used to guide the routing and compaction process. Compaction is done immediately after each level is routed. Experimental results show that the algorithm usually performs 5-10 % better than existing three-layer channel routing algorithms
Keywords
VLSI; circuit layout CAD; MISER; VLSI design; channel router; compacter; gridless; level-graph; three layer; Compaction; Computer science; Constraint theory; Design automation; Grid computing; Partitioning algorithms; Routing; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location
Orlando, FL
ISSN
0738-100X
Print_ISBN
0-89791-363-9
Type
conf
DOI
10.1109/DAC.1990.114943
Filename
114943
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