DocumentCode
2781602
Title
High Performance High-k/Metal Gate Ge pMOSFETs with gate lengths down to 125 nm and halo implant
Author
De Jaeger, B. ; Nicholas, G. ; Brunco, D.P. ; Eneman, G. ; Meuris, M. ; Heyns, M.M.
Author_Institution
lMEC vzw, Leuven
fYear
2007
fDate
11-13 Sept. 2007
Firstpage
462
Lastpage
465
Abstract
Ge pMOSFETs with gate lengths down to 125 nm are fabricated in a Si-like process flow. The addition of a halo implant reduces VT roll-off from 207 mV to 36 mV, and DIBL from 230 mV/V to 54 mV/V. Ion of 770 muA/mum is attained for Ioff of 8.8 nA/mum at VDD = -1.5 V, when evaluating from the source. Benchmarking shows these Ge pMOSFETs have the potential to outperform their (strained) Si counterparts. Measurements at 100degC suggest that Ge will continue to be competitive at realistic logic operating temperatures.
Keywords
MOSFET; benchmark testing; germanium; silicon; Halo implant; benchmarking; germanium; pMOSFET; silicon; Annealing; Doping; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Implants; Logic devices; MOSFETs; Passivation; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European
Conference_Location
Munich
ISSN
1930-8876
Print_ISBN
978-1-4244-1123-8
Electronic_ISBN
1930-8876
Type
conf
DOI
10.1109/ESSDERC.2007.4430978
Filename
4430978
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