DocumentCode
2781622
Title
A genetic algorithm for probe testing problem on high-density PCB
Author
Murakami, Keisuke
Author_Institution
Nat. Inst. of Inf., Tokyo, Japan
fYear
2012
fDate
10-15 June 2012
Firstpage
1
Lastpage
8
Abstract
Printed circuit boards (PCBs) are designed for packing two or more semiconductor chips. On these PCBs, there are various types of faults in the wiring. We must therefore test the PCBs to detect these faults, and it is essential to establish an efficient testing method. One type of test method uses two probes. Two probes, each touching one edge (end) of an inter-chip wiring, are used to check for the presence of faults. Testing is complete when we have confirmed that no faults exist on the PCB. The objective is to minimize the completion time for the testing, that is, our aim is to design efficient routes for the two probes; this is a two-probe routing problem. Several previous studies have proposed an approach involving a two-phase method. Although the two-phase method quickly finds a feasible solution, there is no guarantee that the solution is good. Besides, in recent years, PCB technology provides dense assembly capability and increased chip packaging; this implies that the scale of the two-probe routing problem becomes larger and the problem is difficult to be solved. We therefore propose a new approach, where we formulate a two-probe routing problem as a combinatorial optimization problem and then, we solve the combinatorial optimization problem by using genetic algorithm.We expect that our approach is useful for solving the large-scale problems. In computational experiments, we compare the results of our approach with those obtained using the two-phase method, and we show that our approach outperforms the two-phase method.
Keywords
assembling; chip scale packaging; combinatorial mathematics; fault diagnosis; genetic algorithms; network routing; printed circuit design; printed circuit testing; probes; wiring; PCB technology; assembly capability; chip packaging; combinatorial optimization problem; genetic algorithm; high-density PCB; interchip wiring; printed circuit boards; probe testing problem; semiconductor chips; two-phase method; two-probe routing problem; wiring fault detection; Circuit faults; Genetic algorithms; Pins; Probes; Routing; Testing; Wires; Printed circuit board (PCB); combinatorial optimization problem; fault detection; genetic algorithm; probe testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Evolutionary Computation (CEC), 2012 IEEE Congress on
Conference_Location
Brisbane, QLD
Print_ISBN
978-1-4673-1510-4
Electronic_ISBN
978-1-4673-1508-1
Type
conf
DOI
10.1109/CEC.2012.6253012
Filename
6253012
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