BIST PLAs, pass or fail-a case study

Numerous built-in self-testing (BIST) designs exist for the testing of programmable logic arrays (PLA), but their practical usefulness has not been studied. Several BIST designs were implemented and compared using a common methodology of implementation. A yield analysis is performed to characterize the yield degradation due to the BIST design methodology. Preliminary findings of this work are that the BIST approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for PLAs