DocumentCode
2782296
Title
A digital phase locked loop used in SDH equipment clock
Author
Guowei, Shi ; Qing, Wang ; Ming, Chen
Author_Institution
Northwestern Polytech. Univ., Xian, China
fYear
2000
fDate
2000
Firstpage
231
Lastpage
234
Abstract
The paper introduces the design principle of a highly stable digital phase locked loop used in an SDH equipment clock (SEC), and the chief test results obtained in our lab are reported. The test results show that the digital phase locked loop has the excellent performance to track the reference frequency
Keywords
circuit stability; digital phase locked loops; multiplexing equipment; synchronisation; synchronous digital hierarchy; timing; SDH equipment clock; digital PLL; digital phase locked loop; highly stable PLL; reference frequency tracking; Clocks; Counting circuits; Detectors; Frequency; Phase detection; Phase locked loops; Synchronous digital hierarchy; Timing jitter; Tracking loops; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave and Millimeter Wave Technology, 2000, 2nd International Conference on. ICMMT 2000
Conference_Location
Beijing
Print_ISBN
0-7803-5743-4
Type
conf
DOI
10.1109/ICMMT.2000.895664
Filename
895664
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